The present invention relates to a lead frame and to a semiconductor integrated circuit device using the same. More specifically, the invention relates to technology that can be effectively adapted to semiconductor integrated circuit devices having a resin-molded LSI package.
In order to realize logic LSIs that operate at higher speed and have higher degree of functions, as represented by ASICs (Application Specific Integrated Circuits) such as gate arrays and CBICs (Cell-Based Integrated Circuits), and microcomputers, it is essential to improve a resin-molded LSI package for sealing a logic LSI, e.g., to increase the number of pins, to decrease the thermal resistance and to improve the reliability.
As LSI packages for sealing logic LSI, so far, there has been most extensively used a QFP (quad flat package) having leads along the four sides of the package body, and an ultra-multi-pin QFP has been put into practical use having hundreds of pins of leads.
In the QFP in which the package body is constituted by molding a resin, however, it becomes difficult to efficiently radiate the heat outside the package body as the amount of heat generated by the semiconductor chip increases.
In order to decrease the thermal resistance of the QFP, it has been proposed in which a heat spreader made of a metal plate is buried in a portion of the package body (NIKKEI MICRO DEVICE, Nikkei BP Co., May, 1991, pp. 94-99; NIKKEI ELECTRONICS, Nikkei BP Co., Jan. 21, 1991, pp. 132-136).
According to this technology, the heat spreader is stuck to the back surface of a die pad (tab) of the lead frame for mounting the semiconductor chip followed by molding it with resin, and the heat spreader is exposed from part of the package body. Then, the heat generated in the semiconductor chip is conducted to the heat spreader through the die pad and is radiated from the surface thereof. Thus, there is obtained a QFP having a small thermal resistance.
The QFP is constituted by several members such as semiconductor chip, lead frame and molding resin having different thermal properties (coefficient of thermal expansion, thermal conductivity, etc.), and stress tends to build up inside the package body due to the differences in the thermal properties. In the case of the resin-molded LSI package, in particular, the adhesion is not sufficiently strong in the interface between the lower surface of the die pad and the molding resin, and a large stress tends to build up at the interface.
Therefore, as the outside dimensions of the semiconductor chip mounted on the lead frame (i.e., outside dimensions of the die pad) increases, peeling takes place at the interface between the die pad and the molding resin when the package is heated at a high temperature in the steps of testing temperature cycles and thermal shocks or in the step of solder reflow. Therefore, water and impurities enter the space where peeling has taken place, resulting in the occurrence of cracks in the package and corrosion to the wiring.
To prevent peeling at the interface, it has been known to make a slit of a cross shape in the die pad of the lead frame as disclosed in, for example, Japanese Laid-Open Patent Publication No. 22162/1992. This technique is used for suppressing the peeling at the interface by making a slit in the die pad to bring part of the back surface of the semiconductor chip into direct contact with the molding resin, and by firmly adhering the semiconductor chip to the molding resin.